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SFSU Cryogenic Electronics Group
Thin Film Laboratory
Progress in
developing any integrated circuit device
is made most efficiently when a microfabrication facility is dedicated
to the production of that particular type of device. This is especially
true for our superconducting detectors and amplifiers because they
require
unusual substrates and nonstandard materials. Therefore, in order
to conduct our research efficiently, we have built the San
Francisco
State University Thin Film Laboratory, which is a fully operational
microfabrication
facility having both research and educational missions. It offers
a carefully tailored subset of the spectrum of processes commonly
encountered
in the integrated circuit industry: sputter deposition and
electron-beam
evaporation of metals and insulators, ion etching followed by in
situ
oxidation of surfaces, wet and dry etching, and optical and electron
beam
lithography. Thermal oxidation and doping of silicon using safe
solid
sources are available in an adjacent laboratory. Extremely toxic gases
such as arsine and phosphine are not used in order to maintain a
safe environment. Our thin film evaluation equipment includes a
four
point probe, a stylus profilometer, a transparent film thickness
measurement
system, a CV plotter, and a scanning electron microscope. (A
drawing, showing the layout of the Thin Film Laboratory, can be seen by
clicking on this link.)
The
Thin Film Laboratory owes its existence to the
energy and enthusiasm of San Francisco State students, to the
generosity
of private companies and professional organizations, to assistance from
colleagues at other universities, and to funding from private and
governmental
organizations. We have received valuable new and surplus
equipment
from a large number of corporate
benefactors. The Stanford Center for Integrated Systems, the
U.C. Berkeley Microlab, the Las Positas Vacuum Technology program, and
Lawrence Livermore National Laboratory also have contributed equipment
and expert advice. Primary operating expenses and additional
equipment
funds have been provided by the National Science Foundation RUI, PYI,
and
MRI programs, the NSF Center for Particle Astrophysics, Research
Corporation,
San Francisco State University, Hewlett-Packard Corporation, the
American
Vacuum Society, and by donations from Dr. Neuhauser and Dr. Michael
Taber.
Routine
operations
and
maintenance
are
conducted
by
graduate
and
undergraduate
students who find that type of experience
to be a very marketable part of their technical training. Our
proximity
to Silicon Valley gives us access to a myriad of semiconductor
fabrication
support enterprises whom we hire for specialized servicing of equipment
such as the deionized water system, the scanning electron microscope,
and
the metallurgical microscope. This relieves us of the need to hire a
staff
of full time technicians. Furthermore, many local companies
provide services at little or no cost to us.
The
SFSU
Thin
Film
Laboratory
has
gone
beyond
the
scope
of conventional wafer processing in many areas. For example
we have developed the ability to pattern aligned films on opposite
faces
of substrates up to 8 mm thick. This has been accomplished by
modifying
vacuum chucks for the photoresist spinner and our Quintel Model 2001CT
Manual Tray Load contact printer. We have installed a showerhead
gas distribution/electrode assembly in our plasma etcher in order to
achieve
very uniform etching. We have designed and built a UHV sputtering
system dedicated to the production of tunnel junctions. The
cryopumped
main chamber features an adaptable radial design allowing
side-sputtering
from up to four magnetron sources without breaking vacuum so that clean
interfaces are virtually guaranteed between layers. Ion gun
precleaning
of surfaces and oxidation of tunneling barriers are done in the
turbo-pumped
load lock so that the sputter targets are not exposed to oxygen.
We have made substantial progress in our program to convert an electron
beam direct write system into an instrument for micron-scale
modification
of thin film structures. In order to avoid exorbitant
operational
and maintenance costs, we abandoned the precise stage positioning
fixturing
and instead use the imaging capability to determine the beam location
relative
to alignment marks printed on the wafer during a preceding optical
patterning
step.
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